1. Field
This disclosure relates to methods, systems, and computer program products for debugging in a digital simulation environment.
2. Description of Background
An uninitialized logic or an undefined value at a primary input of a chip design may drive many or all latches of the chip into an undefined state. These problems are found by running multi-valued simulations using a digital simulator. For example, an existing HDL design can be converted into a netlist representation and into a multi-value simulation model. A test case is run using this multi-value simulation model until a checker detects an X state failure. An X state failure is defined as a transition from a defined value to an undefined value in multi-valued simulation. A waveform is generated for all signals in the design for the entire simulation time.
There are many drawbacks to this approach. For example, the approach is time consuming and requires large amounts of storage space. The approach also may need multiple iterations for the following reasons: simulation time increases with model size for creating a waveform of all the signals, since storing the simulation data every cycle becomes a bottleneck and reduces the overall simulation speed; test sequences that run into millions of cycles result in a huge amount of data for the waveform that can not be handled any more by the waveform viewer; and space needed for storing the signal information increases with the number of cycles to run and the model size.
In some cases, simulation may end abruptly with “out of memory” errors. These errors enforce a hard limit on the design size and the number of cycles to record in a waveform and, thus, result in the need for multiple iterations of simulation runs, with each run producing a waveform for a reduced amount of cycles.